Due to advancements in processing technology, complex integrated circuits (ICs) can be designed at various levels of abstraction. Using a hardware description language (HDL), circuits can be designed at the gate level, the register transfer level (RTL), and higher logical levels. When designing using an HDL, the design is often structured in a modular manner. The designer describes each module as a process describing behavior of a system, the behavior describing the generation and propagation of signals through combinatorial logic from one set of registers to another set of registers. HDLs provide a rich set of constructs to describe the functionality of a module. Modules may be combined and augmented to form even higher-level modules.
Prior to implementation, an HDL-based design can be simulated to determine whether the design will function as required. Wasted manufacturing costs due to faulty design may thereby be avoided. Numerous tools are available for simulating circuit designs including, for example, high-level modeling systems (HLMS) and HDL simulators.
Simulation of an HDL-based design includes a compilation phase and a runtime simulation phase. In the compilation phase, HDL source code is input, analyzed, and elaborated to generate executable simulation code. In the runtime simulation phase, the code generated in the compilation phase is executed by a simulation engine to simulate the design. From a user's perspective, HDL simulators work by compiling the HDL-based design once, and then executing the compiled design many times for different sets of input values during the runtime phase. Therefore, the runtime performance of HDL simulators is of critical importance and may be more important than compile time performance in many cases.
An HDL-based design is a hierarchy of modules whose behavior is described by HDL processes. When the HDL-based design is written in VHDL, an HDL process corresponds to either a VHDL process, a concurrent signal assignment, or a concurrent assertion. When the HDL-based design is written in the Verilog language, an HDL process corresponds to either a Verilog always block, an initial block, an assign statement, or a gate. Procedure calls may or may not be regarded as HDL processes. From a hardware perspective, the HDL processes represent hardware that responds to changes in inputs. For example, a change to an output of one circuit may trigger responses in multiple circuits having inputs coupled to the output.
HDL simulators schedule execution of HDL statements such that global variables or signals input to the HDL statements are properly updated and race conditions between concurrent HDL statements are avoided. Simulation of HDL processes is performed over a number of simulation cycles. Each simulation cycle begins with updates to values of nets. Each net, which may be a VHDL signal or a Verilog net, represents values transmitted on a wire of a circuit design. For ease of reference, VHDL signals and Verilog nets may be referred to as either signals or nets, and such terms are used interchangably herein. Each update to a net may trigger a number of processes which model how a hardware implementation of the design would respond. Module processes dependent on the updated nets are scheduled and executed in a delta cycle.
Depending on the circuit design, a net may be changed or updated by the output of multiple module processes. Each process output that may affect the value of a net is referred to as a driver. If a process has several statements that assign values to the same net, only one driver for the net is created per process. The value of the driver is computed from all the values assigned to that net in the process, according to predefined language rules. A net that has at most one driver for each bit is said to be singly-driven. A net that has several drivers on the same set of bits is said to be multiply-driven.
When a net is driven by multiple drivers, a value of the net is determined when nets are updated at runtime using a resolution function. The value computed by the resolution function is referred to as the resolved value, and the resolved value will be assigned as the new value of the net. The process of computing the new value from the driver values of a net is called driver resolution. The resolution function can be standard, defined by the HDL language itself or, for VHDL, can be user-defined.
An HDL specification may include multiple instances of a call to a process. For each instance, the process is simulated using a respective set of nets and respective set of variables. Previous approaches generate a separate portion of code during compilation for each instance of a call to a process. As a result, the amount of simulation code to be executed at simulation runtime and memory requirements can be relatively large.
One or more embodiments may address one or more of the above issues.